A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting new concept of time-mode arithmetic unit (TAU) for phase error extraction. The TAU is time-signal processor that calculates the weighted sum input time offsets. It processes two inputs—the period digitally controlled oscillator (DCO) and instantaneous offset between DCO reference clock edges—and then extracts by calculating their sum. prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In near-integer channel, it shows worst fractional spur below $-$ 59 dBc. Under considerable supply or temperature variations, still remains 51.7 dBc without any background calibration tracking.